1. Technical Field
The present invention generally relates to direct current voltage converters and, more particularly, to a direct current voltage converter which is capable of increasing voltage-boosting efficiency by reducing leakage current.
2. Description of Related Art
In general, voltage converters boost an externally input signal (VCI) N times and then output the signal. In further detail, a charge pump voltage converter boosts the voltage of a unit cell having a MOS transistor and a capacitor to a desired level by cascading the unit cells. The charge pump voltage converter repeatedly pumps the charge of an input signal to the next unit cell in response to a clock signal for charge-pumping so as to boost the voltage. If the voltage converter is realized by a capacitor within an integrated circuit (IC), parasitic capacitance is generated in the voltage converter. Consequently, a leakage current is generated, thus decreasing the voltage-boosting efficiency.
FIG. 1 is a circuit diagram illustrating a conventional charge pump voltage converter 10. The charge pump voltage converter 10 includes capacitors C0, C1, C2, and Cs used for charge-pumping, charge-pumping control signals xcfx86, {overscore (xcfx86)}, xcex8 and {overscore (xcex8)} and PMOS transistors P1, P3, P5 and P7 which respond to the charge-pumping control signals xcex8 and {overscore (xcex8)}.
The charge pumping control signals xcfx86 and {overscore (xcex8)} are signals having a different voltage level from each other or having the same phase. On the other hand, the other pumping control signals {overscore (xcfx86)} and {overscore (xcex8)} are in-phase signals having a different voltage level from each other. Here, {overscore (xcfx86)} and {overscore (xcfx86)} are out of phase and have a predetermined non-overlapped interval (Notm).
If the capacitors C0, C1, and C2 used for charge-pumping are built into an integrated circuit, parasitic capacitances Cp0, Cp1, and Cp2 exist between a plate of the capacitors C0, C1, and C2 and a substrate. The control signal xcfx86 or {overscore (xcfx86)} used for charge-pumping enters one side of the plate of the parasitic capacitances Cp0, Cp1, and Cp2, and a fixed voltage such as, ground (VSS) is input into the other side of the plate. Consequently, each of the parasitic capacitances Cp0, Cp1, and Cp2 serves as a storage capacitor.
FIG. 2 is a diagram illustrating the output waveforms of nodes M0, M1, and M2 constituting the conventional charge pump voltage converter 10 of FIG. 1. With reference to FIGS. 1 and 2, a phenomenon in which a leakage current flows will be described.
The control signals (clocks signals xcfx86 and {overscore (xcfx86)}), which have a predetermined level and swing between an input signal (VCI) and ground (VSS), are input into one plate of the parasitic capacitances Cp0, Cp1, and Cp2. If xcfx86 is VCI and {overscore (xcfx86)} is VSS, then Cp0 and Cp2 are charged to the level of the input signal (VCI). If xcfx86 is changed into VSS and {overscore (xcfx86)} is changed into VCI, then Cp1 is charged to the level of the input signal (VCI) and simultaneously the electric charges of Cp0 and Cp2 (which have already been charged) change to the level of the earth voltage (VSS), thereby generating a leakage current.
Also, if xcfx86 is changed into VCI and {overscore (xcfx86)} is changed into VSS in the next clock phase, Cp0 and Cp2 are charged to the level of the input signal (VCI) and simultaneously the electric charge of Cp1 changes to the level of ground (VSS), thus generating a leakage current again.
In other words, the parasitic capacitances Cp0, Cp1, and Cp2 generate a leakage current by repeating charge and discharge operations in response to clocks signals xcfx86 and {overscore (xcfx86)}. Therefore, the voltage level of each of the nodes M0, M1, and M2 decreases and consequently the level of the boosted voltage decreases.
To solve the above and other problems of the prior art, there is provided a voltage converter which can enhance the voltage-boosting efficiency by decreasing the leakage current.
According to an aspect of the invention, there is provided a voltage converter that includes a first cell, having a first output port, a first node to which a second clock signal is input, and a first capacitor connected between the first output port and the first node. The first cell transmits an input signal to the first output port in response to a first clock signal. A second cell has a second output port, a second node to which an inverse signal of the second clock signal is input, and a second capacitor connected between the second output port and the second node. The second cell transmits a signal of the first output port to the second output port in response to the inverse signal of the first clock signal. A third cell has a final output port and a third capacitor coupled between the final output port and a ground. The third cell transmits a signal of the second output port to the final output port in response to the first clock signal. The first node and the second node are short-circuited in response to a control signal.
According to another aspect of the invention, the first clock signal and the second clock signal are in phase. Moreover, the inverse signal of the first clock signal and the inverse signal of the second clock signal are in phase.
According to yet another aspect of the invention, the first clock signal and the inverse signal of the first clock signal have a non-overlapped interval.
According to still yet another aspect of the invention, the control signal results from performing an exclusive-OR operation on the second clock signal and a signal generated by delaying the second clock signal for a predetermined time and is activated in the non-overlapped interval.
According to a further aspect of the invention, a parasitic capacitance is formed between the first capacitor and the first node or between the second capacitor and the second node.
According to still a further aspect of the invention, the voltage converter is embodied as an integrated circuit.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.